vhdl - Wrong Truth Table for 2 bit comparator using 2 inputs and 3 outputs -

i making 2 bit comparator 2 inputs , 3 outputs. wrote following code in vhdl , when created schematic using xilinx, showed wrong truth tables , k maps of them. here's code:

library ieee; use ieee.std_logic_1164.all;  entity comparator     port ( : in  std_logic_vector(1 downto 0);            b : in  std_logic_vector(1 downto 0);            a_lt_b : out  std_logic;            a_eq_b : out  std_logic;            a_gt_b : out  std_logic); end comparator;  architecture behavioral of comparator  begin  a_lt_b <=    (    b(1) , not a(1))               or(    b(1) ,     b(0) , not a(0))               or(    b(0) , not a(1) , not a(0));  a_eq_b <=    (not b(1) , not b(0) , not a(1) , not a(0))              or (not b(1) ,     b(0) , not a(1) ,     a(0))              or (    b(1) , not b(0) ,     a(1) , not a(0))              or (    b(1) ,     b(0) ,     a(1) ,     a(0));   a_gt_b <=    (not b(1) ,     a(1))              or (not b(1) , not b(0) , a(0))              or (not b(0) ,     a(1)  , a(0));   end behavioral; 

you have written code in pretty obtuse way. why don't write lines like:

a_lt_b <= '1' when unsigned(a) < unsigned(b) else '0'; a_eq_b <= '1' when unsigned(a) = unsigned(b) else '0'; 

to this, need use numeric_std library @ top of file:

use ieee.numeric_std.all; 

with in place, there's far less chance of making mistake of kind have explicit and, not, or combinations (which did not take time check). benefit it's obvious straight away else reading code trying do. lastly, writing code means automatically adapts change in width of operands.

having done this, don't need dig around in resulting schematic check whether tools have done thought would. tools @ mapping code efficiently hardware, can trust them right thing. there few cases can valuable check schematic:

• you want code infer particular element in fpga, example memory or multiplier block; schematic can quick way see has happened.
• there timing closure problem, , want understand how tools have implemented code.
• your device running out of space or using more of particular resource thought; schematic might show, example, discreet registers used, when thought shift register used particular signal.
• the designs works in simulation, not when comes real hardware, , suspect bug in tools. in rare circumstance might able go through schematics , discover bug, it's more in doing this, discover sort of design error. either way schematics can useful in case too.

in summary, use language make simple descriptions of functionality, , trust tools logic optimisation job.